Conjecturing the Revolution’s power

[wraggster]

With Nintendo’s recent announcement that they may never release the technical specifications of their upcoming next-generation console, hardware gurus Ars Technica have made a stab at the possible hardware, including the details of the Revolution’s “broadway” processor. The article is pretty technical, but can be read by anyone with enough time. The author’s approach is pretty novel:

I’m a big fan of drawing conclusions about “overall approach and design philosophy” based on a close look at a processor’s architecture. So what I’ll do here is run that process in reverse, and draw some conclusions about the Revolution’s hardware from the more general guidance that Nintendo has given.
Essentially, from what Miyamoto and Iwata have previously stated in interviews, and from some “inside” information (possibly from IBM, who is manufacturing chips for all 3 next-gen consoles), Nintendo may have the most L2 cache, which in layman’s terms would equate to better code performance with AI, physics, and game control. It fits with Nintendo’s philosophy of developer-friendly environments and their prioritizing of gameplay over graphics. The piece is thorough and makes some interesting conclusions. What do you think of the article’s predictions?

[Cap'n 1time]

These are the leaked specs of nintendos next console:

CPU:
Zilog Z-80A, 4 MHz

RAM:
32K, 64K

Ports:
Two serial ports One parallel port

Display:
Built-in 12" monochrome monitor 40 X 24 or 80 X 24 text.

Storage:
One 500K 8-inch built-in floppy drive. External Expansion w/ 3 floppy bays.

OS:
TRS-DOS, BASIC.