[quote author=guymelef link=board=dcemu;num=1091227578;start=45#55 date=08/01/04 at 02:42:18]hey kamjin, fpga?
funny
pants
golf
association?
I know "if you have to ask, then you probably shouldn't know."
but I am interseted in serious dc hardware mods and not just a fancy case or some silly lights. Â*(personally I think this whole light in your computer case is mildly gay)[/quote]
Hehehe.. FPGA.. that's a good one..
Field Prgrammable Gate arrayis from a family of "logic" devices starting as far back as the PROM, EPROM, PLA, PAL, GAL, CPLD (more acronyms!)
They are basically an array of logic gates (AND, OR, and NOT) with the ability to connect them how you like, in essence you use them to replace a bunch of ttl chips 1 GAL (18pin Generic Logic array) can do the same as about 2-4 TTL chips, as well the method to program them is done though a language like this.. known as HDL
Code:
/** Inputs **/
Pin 1 = inv ;
Pin 2 = and1 ;
Pin 3 = and2 ;
Pin 4 = or1 ;
Pin 5 = or2 ;
Pin 6 = xor1 ;
Pin 7 = xor2 ;
Pin 8 = nand1 ;
Pin 9 = nand2 ;
Pin 10 = GND ;
Pin 20 = VCC ;
/** Outputs **/
Pin 19 = invout ;
Pin 18 = bufout ;
Pin 17 = andout ;
Pin 16 = nandout ;
Pin 15 = orout ;
Pin 14 = norout ;
Pin 13 = bnandout ;
Pin 12 = bandout ;
/** Logic Equations **/
invout = !inv ;
bufout = inv ;
andout = and1 & and2 ;
nandout = !andout ;
orout = or1 #or2 ;
norout = !orout ;
!bnandout = nand1 & nand2 ;
bandout = nand1 & nand2 ;
A FPGA can litterally contain a small CPU, Video chip.. you could litterally put an entire C=64/Apple2 inside on of those, and the language used to program them Verilog/VHDL is almost as though you were programing in C
Here's an example of a 6502's cpu Program counter
Code:
process (clk, reset)
variable pc_add : std_logic_vector(15 downto 0);
variable pc_inc : std_logic_vector(15 downto 0);
begin
if reset='1' then
pc <= "0000000000000000";
elsif clk'event and clk='1' then
pc_add := pc +
(data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in);
pc_inc := pc + '1';
if state=fetch then
pc <= pc_inc;
else
case pc_op is
when MC_NOP => -- Do nothing
when MC_INC => pc <= pc_inc;
when MC_BCC => if c_flag='0' then pc<=pc_add; end if;
when MC_BCS => if c_flag='1' then pc<=pc_add; end if;
when MC_BEQ => if z_flag='1' then pc<=pc_add; end if;
when MC_BNE => if z_flag='0' then pc<=pc_add; end if;
when MC_BMI => if n_flag='1' then pc<=pc_add; end if;
when MC_BPL => if n_flag='0' then pc<=pc_add; end if;
when MC_BVC => if v_flag='0' then pc<=pc_add; end if;
when MC_BVS => if v_flag='1' then pc<=pc_add; end if;
when MC_SPLIT => pc <= data_in & dint1;
when others => -- Do nothing
end case;
end if;
end if;
end process;
Hope this this explains more then it confuses..
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