Cz80_Exec(&Cz80_struc,228); => z80_emulate(228);
Cz80_Reset(&Cz80_struc); => z80_reset();
Cz80_Clear_IRQ(&Cz80_struc); => z80_lower_IRQ();
Cz80_Set_IRQ(&Cz80_struc, 0); => z80_raise_IRQ(0);
Cz80_struc.CycleIO => z80_get_cycles_elapsed() ?
Cz80_Set_IRQ_Callback(&Cz80_struc,sms_irq_callback ); => ??
Cz80_Set_Fetch(&Cz80_struc, 0x8000, 0xBFFF, (u32)&sms.sram[offset]); => z80_map_fetch(0x8000, 0xBFFF, (u32)&sms.sram[offset]);
Cz80_Set_ReadB(&Cz80_struc,&cpu_readmem8); => z80_add_read(0x0000, 0xFFFF, Z80_MAP_HANDLED, &cpu_readmem8);
Cz80_Set_WriteB(&Cz80_struc,&cpu_writemem8); => z80_add_write(0x0000, 0xFFFF, Z80_MAP_HANDLED, &cpu_writemem8);
Cz80_Set_INPort(&Cz80_struc,(CZ80_READ *)&cz80_z80_readport16); => z80_set_in(&cz80_z80_readport16);
Cz80_Set_OUTPort(&Cz80_struc,(CZ80_WRITE *)&cz80_z80_writeport16); => z80_set_out(&cz80_z80_writeport16);
Cz80_Init(&Cz80_struc); => z80_init_memmap();
Cz80_Set_Fetch(&Cz80_struc,0x0000,0x3FFF,(u32)((vo id *)&cart.rom[0x0000])); => z80_map_fetch(0x0000, 0x7FFF, (u32)&cart.rom[0x0000]);
.. => z80_end_memmap();
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