Stef wrote:
yes, that's one of the first things that came to my mind aswell, however, I shunned it because you would need a 1024 lenght jump table, since the combinations are 'a8 xy8', 'a16 xy16', 'a8 xy16', 'a16 xy8', but thinking about it, you're right, you could designate a register for the instruction table offset and set that offset to the correct jump table index (256*n) at each sep/rep instruction (if I remember the sep/rep stuff, this was ages ago).then we have a 512 lenght jump table, where firsts 256 entries are for 8 bits instructions and lasts 256 for 16 bits ones
I don't know if that could be really applied to the 65816 cpu, but anyway i'm sure we can always find a solution.
either way, I'm sure the dreamsnes guys thought of a smart way, looking forward to examining their sh4 65816 emulator.
sounds great, btw what toolchain are you using, and is anyone using gcc3.4.0 branch/snapshots and has examined output of -O4? does any optimization increases carry over to the sh4?I already compared asm generated by GCC against my own asm file and really, we do easily better... specially for the SH-4 cpu where we have many available registers.
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