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Thread: Overclocking the DC and where to get the Increase

                  
   
  1. #21

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    Oh crap. I totally misinterpreted that. Get ready for long ass post, strted off by my reply to what he said X.X

    "> VERY interesting. I had no idea the so-called "GPU" pin was actually
    > the FSB pin. I appreciate the information. So what your saying, is
    > that to make overclocking the CPU more possible, I would also possibly
    > have to raise the FSB so that the CPU doesn't go out of sync?

    I think you have misunderstood what I wrote. Forget about that 54MHz "GPU"
    pin for a moment. Here's a simplified clock diagram (use fixed width
    font to view properly):

    .-------. .---------------.
    | Xtal | | SH4 |
    | 13.5M | .---+--+---x6-CORE | .------------.
    `---+--' | | | 200M | | SDRAM |
    | | | | | 100M | Main mem. |
    .---+------. | | `---x3-------+---+---------+ 100MHz |
    | PLL | | | 100M | | | |
    | 54M 33M | | `---------------' |100M `------------'
    `--+----+--' | .-------------------+------. .------------.
    | | | | Holly | | | SDRAM |
    | `----' | (System ASIC) .--+---. | | Video mem. |
    `-------------+---. | `-+--+ 100MHz |
    | | .-------+----. | | |
    | /n | PowerVR | | `------------'
    | | | 100MHz | |
    | | `------------' |
    `---+----------------------'
    |13.5M/27M
    .---+---.
    | Video |
    | DAC |
    `-------'

    As you can see, the 33MHz clock is multiplied by 6 inside the SH4 to
    generate its core operating frequency of 200MHz. It is also multiplied by
    3 to generate a 100MHz clock that in your terminology might be called the
    "FSB" clock.

    This "FSB" clock is used to drive the SDRAM and most stuff in Holly
    (including the GPU). Since the 100MHz is generated by multiplying the
    33MHz clock by 3, if you change the input to 50MHz to get a 300MHz CPU
    clock, the "FSB" clock will be half of that ie 150MHz instead!

    Listen to what Simon said: the GPU limit might well be 133MHz (and since
    he designed the damn chip, you might want to consider he knows what he's
    talking about!). If the GPU is running at 133MHz, the SH4 will be running
    at twice that, namely 266MHz, which is close to the limit you state:
    270MHz. So it seems quite probable to me that it's not the SH4 that is
    the limiting factor. It very well could be the GPU!

    Returning to that 54MHz "GPU" clock now. As you can see it is not really a
    "GPU" clock at all; it is more properly termed "pixel clock" since it is
    used to drive the video encoder/DAC. The 54MHz pixel clock is not
    multiplied by 2 (as I've seen asserted); it is actually divided by a
    divisor n that is controlled by bit 23 in hardware register a05f8044:

    bit 23
    ------
    0: n = 4 (pixel clock=13.5MHz NTSC/PAL mode)
    1: n = 2 (pixel clock=27MHz VGA mode)

    So overclocking this clock will do little to increase the GPU speed. It
    will only screw up the refresh rates so the signal is no longer NTSC/PAL
    compatible

    > But yeah, still looking for the 1.8v thing-a-ma-doo-dad.

    I'm **GUESSING** that IC104 **MIGHT** be the one to generate the 1.8V. It's a
    five-pin 1.5-7V variable voltage regulator that you'll find it on the
    flip side of the PCB, near the SH4 but further towards the edge. I would
    not recommend you to attempt anything drastic without being sure you know
    what you're doing, and if anything goes wrong, don't blame me!"

    So in fact, the GPU/FSB pin only controls the pixel clock, not either the GPU nor the FSB. The *CPU* pin controls EVERYTHING.

  2. #22
    DCEmu Pro Cross's Avatar
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    lol, more info to the flame. Well lets see where this takes us

  3. #23
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    again that explains alot, i have to say congrats for finding this out, so many people are completely wrong about what those generated clocks do.

    Who is telling you all this btw?

  4. #24
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    This was just being discussed on the DCdev mailing list, so i assume it was from there.

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    That would be Lars Olsson from the DCDev list on Yahoo.

  6. #26
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    I see, how do you get on that mailing list?

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    You'll need an account on Yahoo Groups, go to http://groups.yahoo.com, then search for DCDev or just use this link http://groups.yahoo.com/group/dcdev/

  8. #28

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    yeah, just go there and sign up, then you are put on the mailing list. The "group" is basically a single forum where people post in depth information or questions about the hardware/software of the Dreamcast. And every reply is sent through the mailing list, and is posted, so you know asap.

    Pretty cool stuff. I got forwarded there by Dan Potter, and yes it was Lars who replied.

    So basically, anyone with a voltometer or the like, would you mind testing IC104 on the bottom of the Dreamcast motherboard? Its only 5 pins, so it shouldn't take long.

  9. #29
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    You don't have a multimeter and yet your doing all this? lol.

    Yeah the pinout is:
    Code:
     IC 104 
     ________
    |         |
    |         |
    |         |
     5 4 3 2 1
    1: ground
    2: 1.24V
    3: 1.99V
    4: 3.24V
    5: 3.24V

    thats what my multimeter said, no 1.8V though, perhaps Sega underclocked the SH-4? so maybe its the 1.24V?

  10. #30

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    Nah, the SH4 isnt underclocked that i can tell. The official SH4 product thingamajigger from Hitachi says its 200MHz. Odds are, either the DC version is a low power version (seeing how is hard coded low-endian) or perhaps it gets more juice to keep it more stable. I would doubt the assertion of more juice, since that would have increased the amount of heat, then again, that explains how the DC can hit a nearly 40% overclock without a voltage increase, something impossible on any other processor I have ever seen.

    So, odds are, its probably the 1.99v lead, unless there is still another circuit on the DC motherboard that we don't know about. But I doubt that since I am almost certain that the 3.24v leads are for the I/O voltage. Btw, did you find how many amps or amp increments that thos pins run at? I don't wanna blow the circuit overloading on amps.

    Nice finds there ptr!

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